Dual speed readout integrated circuit for high spatial and temporal resolution applications
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United States of America Patent
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Apr 22, 2014
Grant Date -
May 3, 2012
app pub date -
Oct 27, 2011
filing date -
Oct 27, 2010
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Abstract
A dual speed Read-Out Integrated Circuit employs a native pixel array with associated high resolution integration circuits for each pixel and a superpixel array created within the native pixel array by combination of native pixels for charge sharing integration in reduced resolution integration circuits simultaneously with the integration of the high resolution integration circuits. Switching control for readout of the high resolution integration circuits is accomplished at a first frame rate and switching control for readout of the reduced resolution integration circuits is accomplished at a second higher frame rate.
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