Method for overcoming livelock in a multi-threaded system
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United States of America Patent
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May 6, 2014
Grant Date -
Aug 6, 2009
app pub date -
Jan 31, 2008
filing date -
Jan 31, 2008
priority date (Note) -
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Abstract
A microprocessor pipeline arrangement 1 includes a plurality of functional units P1, P2, P3, . . . , PN. A number of the functional units P1, P3, PN have access to a respective cache memory C1, C3, CN from which it can retrieve data needed to process threads that pass through the pipeline. The pipeline arrangement 1 also includes a number of monitors to determine when the system enters a state of livelock (e.g. inter-cache livelocks, intra-cache livelocks and/or “near-livelock” situations): a top-level monitor MT to detect livelock situations in the pipeline as a whole; and second-level (“local”) monitors M1 and M3 associated with individual caches C1 and C3.
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