High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
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United States of America Patent
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May 20, 2014
Grant Date -
Oct 4, 2012
app pub date -
Jun 15, 2012
filing date -
Mar 8, 2008
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Abstract
Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
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