Patterning of submicron pillars in a memory array
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United States of America Patent
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Jun 24, 2014
Grant Date -
Sep 10, 2009
app pub date -
Apr 10, 2009
filing date -
Feb 17, 2005
priority date (Note) -
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Abstract
Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.
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