Memory access consolidation for SIMD processing elements using transaction identifiers
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United States of America Patent
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Jun 24, 2014
Grant Date -
Feb 28, 2008
app pub date -
Jun 29, 2007
filing date -
Apr 9, 1999
priority date (Note) -
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Abstract
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.
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