Method and apparatus for diagnosing a fault of a memory using interim time after execution of an application

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United States of America Patent

PATENT NO 8762926
APP PUB NO 20140095949A1
SERIAL NO

13754444

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Abstract

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An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amaki, Satoru Tokyo, JP 4 13
Nakatani, Hiroshi Tokyo, JP 105 856
Ohnishi, Naoya Tokyo, JP 10 25
Sameda, Yoshito Kanagawa-ken, JP 19 123
Toko, Makoto Saitama-ken, JP 12 79

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