Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
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United States of America Patent
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Jul 1, 2014
Grant Date -
Sep 29, 2011
app pub date -
Jun 6, 2011
filing date -
Oct 30, 2007
priority date (Note) -
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Abstract
Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
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