Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression
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United States of America Patent
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Jul 1, 2014
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N/A
app pub date -
Mar 29, 2013
filing date -
Mar 15, 2013
priority date (Note) -
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Abstract
Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.
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