Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
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United States of America Patent
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Jul 1, 2014
Grant Date -
N/A
app pub date -
Dec 18, 2012
filing date -
Dec 18, 2012
priority date (Note) -
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Abstract
Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.
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