Automatic Generation of Wire Tag Lists for a Metal Stack
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United States of America Patent
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Jul 1, 2014
Grant Date -
Jul 10, 2014
app pub date -
Jan 9, 2013
filing date -
Jan 9, 2013
priority date (Note) -
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Abstract
Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.
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