Virtual machine hardware for RISC and CISC processors
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United States of America Patent
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Jul 1, 2014
Grant Date -
Oct 27, 2005
app pub date -
Jun 29, 2005
filing date -
Aug 24, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
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