Programming to mitigate memory cell performance differences
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United States of America Patent
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Jul 8, 2014
Grant Date -
Jun 27, 2013
app pub date -
Feb 25, 2013
filing date -
Aug 18, 2010
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Abstract
Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage.
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