Method for improving static timing analysis and optimizing circuits using reverse merge
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United States of America Patent
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Jul 8, 2014
Grant Date -
Jul 19, 2012
app pub date -
Jan 14, 2011
filing date -
Jan 14, 2011
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Abstract
Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.
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