Low power oversampling with delay locked loop implementation
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United States of America Patent
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Jul 15, 2014
Grant Date -
Dec 26, 2013
app pub date -
Jun 25, 2012
filing date -
Jun 25, 2012
priority date (Note) -
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Abstract
In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.
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