Graphics render clock throttling and gating mechanism for power saving

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8780121
APP PUB NO 20110148887A1
SERIAL NO

12908308

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Abstract

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An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chong, Lai Kuan Penang, MY 1 12
Tang, Lai Guan Penang, MY 34 85

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