Memory devices having data lines included in top and bottom conductive lines
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United States of America Patent
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Jul 15, 2014
Grant Date -
Feb 27, 2014
app pub date -
Aug 21, 2012
filing date -
Aug 21, 2012
priority date (Note) -
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Abstract
Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described.
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