Memory device and system including a memory device electronically connectable to a host circuit
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United States of America Patent
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Jul 15, 2014
Grant Date -
Oct 7, 2010
app pub date -
Mar 31, 2010
filing date -
Apr 1, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A memory includes a nonvolatile memory cell array, and a memory control circuit which carries out writing of data to and reading of data from the memory cell array in access units of N bits where N is an integer equal to 2 or greater. The memory cell array includes a rewritable area in which both writing of data and reading of data are permissible, and a read-only area in which writing of data is prohibited and reading of data is permissible. The rewritable area is configured so that the N bits constituting one access unit contain both actual data and an error detection code. The read-only area is divided between an actual data area in which the N bits constituting one access unit contain actual data, and an error detection code area in which the N bits constituting one access unit contain error detection codes.
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