Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor
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United States of America Patent
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Jul 15, 2014
Grant Date -
Jun 3, 2010
app pub date -
Dec 2, 2008
filing date -
Dec 2, 2008
priority date (Note) -
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Abstract
Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
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