Hierarchical channel marking in a memory system
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United States of America Patent
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Jul 15, 2014
Grant Date -
Jul 25, 2013
app pub date -
Jan 19, 2012
filing date -
Jan 19, 2012
priority date (Note) -
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Abstract
Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
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