CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials
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United States of America Patent
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Jul 22, 2014
Grant Date -
Jun 7, 2012
app pub date -
Feb 9, 2012
filing date -
May 31, 2006
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Abstract
Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
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