Non-planar semiconductor device having channel region with low band-gap cladding layer
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United States of America Patent
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Jul 22, 2014
Grant Date -
Mar 27, 2014
app pub date -
Sep 27, 2012
filing date -
Sep 27, 2012
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Abstract
Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
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