Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections
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United States of America Patent
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Aug 5, 2014
Grant Date -
Jan 23, 2014
app pub date -
Jul 20, 2012
filing date -
Jul 20, 2012
priority date (Note) -
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Abstract
A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
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