System on chip and transmission method under AXI bus
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United States of America Patent
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Aug 5, 2014
Grant Date -
Dec 1, 2011
app pub date -
Apr 4, 2011
filing date -
May 31, 2010
priority date (Note) -
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Abstract
A system on chip (soc) and A transmission method under Advanced eXtensible Interface (AXI) bus are disclosed. The system includes a master device, a first extending module, a first interconnection structure, a first subtracting module, a second interconnection structure, and a slave device. The first extending module is configured to add N bits into an identifier (ID) carried in a transmission request, where N is equal to a sum of bits added by all interconnection structures in a longest loop of a system into the ID carried in the transmission request that passes through the interconnection structures. The first subtracting module is configured to subtract M bits from the ID carried in the transmission request output by the first interconnection structure when a slave device to be accessed by the master device is not a slave device connected with the first interconnection structure, where M is equal to the number of bits added by the first interconnection structure into the ID carried in the transmission request that passes through the first interconnection structure. The embodiments reduce costs and avoid the problems caused by ID compression.
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