Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration
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United States of America Patent
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Aug 5, 2014
Grant Date -
Aug 8, 2013
app pub date -
Feb 8, 2012
filing date -
Feb 8, 2012
priority date (Note) -
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Abstract
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.
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