Memory with three transistor memory cell device

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United States of America Patent

PATENT NO 8804424
SERIAL NO

13217867

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Abstract

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Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feeley, Peter Boise, US 159 1027
Sakui, Koji Tokyo, JP 278 4187

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