Apparatus and methods to provide power management for memory devices
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United States of America Patent
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Aug 12, 2014
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app pub date -
Sep 6, 2012
filing date -
Sep 6, 2012
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Abstract
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
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