Graphene transistors with self-aligned gates
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United States of America Patent
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Aug 19, 2014
Grant Date -
Nov 14, 2013
app pub date -
May 10, 2012
filing date -
May 10, 2012
priority date (Note) -
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Abstract
Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel.
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