Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of die
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United States of America Patent
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Aug 26, 2014
Grant Date -
May 26, 2011
app pub date -
Feb 7, 2011
filing date -
May 4, 2007
priority date (Note) -
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Abstract
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.
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