Process charging protection for split gate charge trapping flash
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United States of America Patent
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Aug 26, 2014
Grant Date -
Jun 19, 2014
app pub date -
Dec 14, 2012
filing date -
Dec 14, 2012
priority date (Note) -
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Abstract
A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
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