System and methods for converting planar design to FinFET design

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8816444
SERIAL NO

13416862

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Chih-Sheng Hsinchu, TW 201 4166
Chen, Chung-Hsien Taipei, TW 28 2097
Ko, Ting-Chu Hsinchu, TW 34 1216
Lin, Yi-Tang Hsinchu, TW 67 2062
Shieh, Ming-Feng Yongkang, TW 120 6593
Wann, Clement Hsingjen Carmel, US 290 15319

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Feb 26, 2026
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00