Electrical signal isolation and linearity in SOI structures
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United States of America Patent
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Aug 26, 2014
Grant Date -
Jul 18, 2013
app pub date -
Aug 8, 2012
filing date -
Jan 13, 2012
priority date (Note) -
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Abstract
Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
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