Method and system for concurrently locating systematic bits and parity bits in physical channel memory to increase HARQ processing speed in 3GPP CPC system
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United States of America Patent
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Aug 26, 2014
Grant Date -
Jun 23, 2011
app pub date -
Apr 27, 2010
filing date -
Dec 18, 2009
priority date (Note) -
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Abstract
A UE receives a HS-PDSCH transmission from a base station and concurrently performs rate matching on systematic bits and parity bits (parity 1 bits, parity 2 bits) of the received HS-PDSCH transmission. The systematic bits and parity bits are buffered in a CPC circular buffer to support HARQ processing in a HS-SCCH-less operation of the base station. Memory locations are computed for the systematic bits and the parity bits according to corresponding transmission parameters such as, for example, redundancy version, number of systematic bits and/or number of physical channels. The systematic bits and the parity bits are stored in the corresponding computed memory locations of the CPC circular buffer. At least a portion of the stored systematic bits and parity bits are concurrently generated based on corresponding transmission parameters from the CPC circular buffer per request to support concurrent rate matching on systematic bits and parity bits.
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