Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
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United States of America Patent
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Aug 26, 2014
Grant Date -
Jun 28, 2012
app pub date -
Dec 22, 2011
filing date -
Dec 22, 2011
priority date (Note) -
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Abstract
Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.
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