ESD analysis apparatus

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United States of America Patent

PATENT NO 8819614
APP PUB NO 20140013296A1
SERIAL NO

13760943

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Abstract

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According to one embodiment, a chip model generating unit and a counter tester ground capacitance adding unit are provided. The chip model generating unit generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added. The counter tester ground capacitance adding unit adds a counter tester ground capacitance to the chip model.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hayashi, Sachio Kanagawa, JP 15 102

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