Method of fabricating a flash memory comprising a high-K dielectric and a metal gate
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United States of America Patent
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Sep 2, 2014
Grant Date -
Feb 6, 2014
app pub date -
Oct 10, 2013
filing date -
Nov 6, 2009
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Abstract
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
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