Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof
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United States of America Patent
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Sep 2, 2014
Grant Date -
Jun 14, 2012
app pub date -
Dec 12, 2011
filing date -
Dec 14, 2010
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Abstract
A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.
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