Memory disambiguation hardware to support software binary translation
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United States of America Patent
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Sep 2, 2014
Grant Date -
Oct 3, 2013
app pub date -
Mar 30, 2012
filing date -
Mar 30, 2012
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Abstract
A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
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