Methods of forming bulk FinFET devices by performing a recessing process on liner materials to define different fin heights and FinFET devices with such recessed liner materials

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United States of America Patent

PATENT NO 8835262
APP PUB NO 20140191324A1
SERIAL NO

13736294

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Abstract

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One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

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Patent Owner(s)

  • AURIGA INNOVATIONS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cai, Xiuyu Niskayuna, US 195 3734
Cheng, Kangguo Schenectady, US 3065 29546
Khakifirooz, Ali Mountain View, US 841 11850
Xie, Ruilong Niskayuna, US 1408 10665

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