Structure and method to form input/output devices
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United States of America Patent
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Sep 16, 2014
Grant Date -
Feb 13, 2014
app pub date -
Aug 13, 2012
filing date -
Aug 13, 2012
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Abstract
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
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