Structure and method for making low leakage and low mismatch NMOSFET
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United States of America Patent
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Sep 16, 2014
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app pub date -
Mar 14, 2013
filing date -
Jan 21, 2010
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Abstract
An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
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