Use of logic circuit embedded into comparator for foreground offset cancellation
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United States of America Patent
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Sep 16, 2014
Grant Date -
Jun 20, 2013
app pub date -
Dec 20, 2011
filing date -
Dec 20, 2011
priority date (Note) -
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Abstract
A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.
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