Translation layer in a solid state storage device
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United States of America Patent
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Sep 16, 2014
Grant Date -
Apr 15, 2010
app pub date -
Oct 13, 2008
filing date -
Oct 13, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
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