Atomic-operation coalescing technique in multi-chip systems
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United States of America Patent
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Sep 16, 2014
Grant Date -
Oct 17, 2013
app pub date -
Jun 10, 2013
filing date -
Feb 17, 2009
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Abstract
A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
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