Automated control of opening and closing of synchronous dynamic random access memory rows

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United States of America Patent

PATENT NO 8842480
SERIAL NO

13569276

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Abstract

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An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ellis, Jackson L Fort Collins, US 30 876
Sinha, Shruti Maharashtra, IN 3 42

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