Multi-dimension memory timing tuner
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United States of America Patent
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Sep 23, 2014
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N/A
app pub date -
Mar 6, 2014
filing date -
Jul 7, 2010
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Abstract
In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a bus, such as a data control system, system bus, or memory bus. Memory maintains values, such as a control register maintaining control register values, which are adjustable to tune bus timing margins in multi-dimensions. The bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the values to tune the bus timing margins in the multi-dimensions.
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