Collecting debug data in a secure chip implementation
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United States of America Patent
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Sep 23, 2014
Grant Date -
Jan 31, 2013
app pub date -
Jun 12, 2012
filing date -
Jul 28, 2011
priority date (Note) -
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Abstract
Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.
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