Memory error protection using addressable dynamic ram data locations
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United States of America Patent
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Sep 23, 2014
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N/A
app pub date -
Mar 16, 2012
filing date -
Mar 16, 2012
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Abstract
In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.
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