Content addressable memory data clustering block architecture
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United States of America Patent
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Sep 30, 2014
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N/A
app pub date -
Dec 22, 2011
filing date -
Dec 22, 2011
priority date (Note) -
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Abstract
An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.
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