Operation of a dual instruction pipe virus co-processor

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United States of America Patent

PATENT NO 8850586
SERIAL NO

14266672

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Abstract

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Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a content object is stored by a general purpose processor to a system memory. The memory has stored therein a page directory containing information for translating virtual addresses to physical addresses. Multiple most recently used entries of the page directory are cached, by a virus co-processor, within translation lookaside buffers (TLBs) implemented within an on-chip cache of the co-processor. Instructions are read by the co-processor, from a virus signature memory of the co-processor. The instructions contain op-codes of a first and second instruction type. Instructions of the first type are assigned to a first instruction pipe of the co-processor. An instruction assigned to the first instruction pipe is executed including accessing the content object by performing direct virtual memory addressing of the system memory and comparing the content object against a string.

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Patent Owner(s)

  • FORTINET, INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Lin Fremont, US 215 1947
Xie, Michael Palo Alto, US 132 2189
Zhou, Xu San Jose, US 90 754

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