Self-adjusting gate hard mask
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United States of America Patent
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Oct 7, 2014
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app pub date -
Jan 31, 2013
filing date -
Jan 31, 2013
priority date (Note) -
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Abstract
A method provides an intermediate semiconductor device structure and includes providing a wafer having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non-planar wafer surface topography due at least to a presence of the first dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.
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